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Please use this identifier to cite or link to this item: http://hdl.handle.net/1813/10755
Title: High Performance Techniques for Reducing Cache Power
Authors: Bhadauria, Major
Keywords: performance
power
cache
memory
Issue Date: 30-Apr-2008
Abstract: Minimizing power consumption continues to grow as a critical design issue for many platforms, from embedded systems to chip multiprocessors (CMP) to ultra scale parallel systems. Embedded systems, like their desktop counterparts, have migrated to a multicore architecture. Power is a first-order design component in the embedded domain, and advances in process technology have led to a cascading effect. Chiefly, decreasing feature sizes have led to lower voltage thresholds (to retain performance), thereby resulting in exponential increases in leakage. Leakage has now become a fundamental design concern with respect to total power budget. This issue has been postponed by using different SRAM cell designs on current process technologies. Two approaches have been proposed to reduce the power requirements of cache memories: voltage scaling (or "drowsiness") and partitioning. Voltage scaling targets leakage current by reducing the voltage to cache lines unlikely to be referenced soon. Partitioning targets dynamic switching power by splitting the cache into smaller structures, either banks or regions. We combine the best of these two approaches by developing a new region cache organization. We add a new voltage scaling design that enables finer control of cache lines than previous voltage scaling policies. We evaluation this new organization on embedded and high performance architectures, finding it provides similar high performance and much lower power consumption than previously published low-power cache designs.
URI: http://hdl.handle.net/1813/10755
Appears in Collections:Theses and Dissertations (OPEN)

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