Skip to main content


eCommons@Cornell

eCommons@Cornell >
Cornell University Graduate School >
Theses and Dissertations (OPEN) >

Please use this identifier to cite or link to this item: http://hdl.handle.net/1813/13528
Title: Exploring The Microarchitectural Behavior Of An Industrial Processor In The Presence Of Transient Faults
Authors: Trammell, Catherine
Issue Date: 19-Aug-2009
Abstract: Soft errors are an ubiquitous, ever-increasing problem that will compromise future computing integrity at every echelon. Many architectures provide protection from these transient events for large arrays, such as register ?les and caches, but often, little is done to protect common latches from corruption, such as those used in con?guration and in the pipeline. It is important that we identify the most vulnerable processor components at the latch level, so as to mitigate soft errors before they manifest in architectural state. This research evaluates the vulnerability of latches within an IBM PowerPC-based processor core. We simulate a VHDL model of the processor and use an RTX error injection methodology to inject bit-?ips into the latch output nets at runtime. We then perform an analysis of the system?s behavior while executing various TST applications, paying particular attention to the ?oating point unit, and propose solutions to increase processor robustness.
URI: http://hdl.handle.net/1813/13528
Appears in Collections:Theses and Dissertations (OPEN)

Files in This Item:

File Description SizeFormat
Trammell, Catherine.pdf1.18 MBAdobe PDFView/Open

Refworks Export

Items in eCommons are protected by copyright, with all rights reserved, unless otherwise indicated.

 

© 2014 Cornell University Library Contact Us