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Please use this identifier to cite or link to this item: http://hdl.handle.net/1813/2503
Title: Ultra Narrow Silicon FETs Integrated With Microfluidic System for Serial Sequencing of Biomolecules Based on Local Charge Sensing
Authors: Gokirmak, Ali
Keywords: Silicon
MOSFET
narrow
DNA
charge
sensing
scaling
FLASH
memory
confinement
STI
isolation
nitride
side-gate
capacitance
C-V
aF
fF
atto
femto
nano
fluidic
microfluidic
protein
RNA
CMOS
FET
short
DIBL
MOS
sequencing
sequence
Issue Date: 22-Nov-2005
Abstract: Ultra-narrow channel silicon field effect transistors (FET) with suspended gates, integrated with on-chip micro-fluidic delivery system are demonstrated. These devices are designed to be used for serial sequencing of DNA, RNA and proteins, by detecting the local charge variations along these molecules as they are passed between the gate and the channel of the FETs in an aqueous solution. Devices are fabricated with down to 5 nm high tunnels passing between the gate and the channel of the FETs, integrated with larger scale micro-fluidic delivery system. The smallest fabricated active area width is less than 10 nm. A silicon nitride based shallow trench isolation (STI) scheme is developed in order to accommodate fabrication of the tunnels going through the FET, through removal of sacrificial silicon dioxide in HF. A device architecture with an independently controlled side-gate, surrounding the active area, is developed to suppress the edge related leakage currents and allow further scaling of the device width while achieving high sensitivity. The side-gated devices are fabricated as nFET prototypes using thermally grown silicon dioxide gate insulator and silicon nitride STI. The leakage currents are suppressed below 50 fA down to 70 nm gate length with the application of a negative side-gate bias. Side-gated sub-10 nm wide devices exhibit threshold voltage tunability in a range exceeding 2.5 V and with a maximum sensitivity of ?Vt/?Vside > 2 V/V. Wider channel devices with gate lengths less than 70 nm retain Ion/Ioff ratios exceeding 109 and achieve drive currents exceeding 1.5 mA/?m. Narrow channel devices with 150 nm gate length show less than 5 mV/V drain induced barrier lowering. With these performance parameters, side-gated device geometry is a promising candidate for future generation low-power, and higher performance circuits. The possibility of using this device geometry as a side-trapping FLASH memory structure is also demonstrated. A capacitance measurement technique is developed to achieve aF resolution using an instrument with 0.1 fF resolution at 1 MHz utilizing the random fluctuations. These capacitance measurements, performed on the small scale devices, are used to extract effective device dimensions, carrier density and effective carrier mobilities.
URI: http://hdl.handle.net/1813/2503
Appears in Collections:Theses and Dissertations (OPEN)

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