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Please use this identifier to cite or link to this item: http://hdl.handle.net/1813/29158
Title: Nanophotonic Interconnect Architectures For Many-Core Microprocessors
Authors: Cianchetti, Mark
Keywords: Nanophotonics
Interconnection networks
Communication networks
Issue Date: 31-Jan-2012
Abstract: Nanophotonics is an emerging technology that has the potential to improve the performance and energy consumption of inter- and intra-die communication in future chip multiprocessors. To date, the successful demonstration of a working large-scale system has been hampered by integration challenges and temperature sensitivity of the optical building blocks. Moreover, current approaches to interfacing with these devices are either CMOS incompatible or degrade the potential Tb/s modulation capability to only tens of Gb/s. At first glance it may seem like all of these challenges hint at today's nanophotonic devices being too impractical. However, using a combination of proposed solutions at the device and architectural level, a rich tradeoff space begins to emerge that is still largely untouched due to the knowledge gap between nanophotonic researchers on both sides of the spectrum. To this end, this dissertation attempts to fill this gap by targeting both device and system level research in an integrated fashion. We begin with an extended background and related work section that presents the relevant parameters and functionality of key optical devices for designing interconnection networks at the architecture level. Following this, we give a detailed discussion on the system level implications of optics including communication methods and summaries of recent network architectures for both on-chip and off-chip signaling with important takeaways for designing future systems. The lack of a comprehensive and accurate modeling strategy for optical com- ponents in the architecture community has lead to potentially inaccurate, and inflated, power and performance estimates. Since better representation of optical devices in architectural level simulations is essential to producing trustworthy results, we present a comprehensive, mathematical model for all of the major optical building blocks. To our knowledge, this is the first comprehensive model of all relevant optical devices specifically tailored to system level design for architects. An interesting aspect of architectural research in the field of optics is that there is not a natural progression of scaling parameters that will necessarily dictate future designs as is the case in CMOS. Because nanophotonics is an emerging technology, the potential is limitless for creating new devices that solve previous challenges. Optical packet switching is a promising approach for overcoming the performance and power limitations of bus-based on-chip networks. We present two variations of Phastlane, the first proposed nanophotonic packet switched architecture. In our evaluation, we demonstrate the potential improvements in system performance and power consumption across a range of modulator and receiver parameters. We also augment this analysis with projections for current optical devices using our mathematical device model. Finally, we propose alternatives for overcoming some of the limitations of both Phastlane architectures in the event that future optical components stagnate at current performance and power consumption. Also, we use our device model to explore a less aggressive approach to nanophotonics that judiciously combines electrical and optical interconnect.
Committee Chair: Albonesi, David H.
Committee Member: Batten, Christopher
Suh, Gookwon Edward
Discipline: Electrical Engineering
Degree Name: Ph.D. of Electrical Engineering
Degree Level: Doctor of Philosophy
Degree Grantor: Cornell University
URI: http://hdl.handle.net/1813/29158
Appears in Collections:Theses and Dissertations (OPEN)

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