ROPE: A New Twist in Computer Architectures

Abstract

Supercomputer architectures are not as fast as logic technology allows because memories are slow than the CPU, conditional jumps limit the usefulness of pipelining and prefetching mechanisms, and functional-unit parallelism is limited by the speed of hardware scheduling. We propose a supercomputer architecture called Ring Of Prefetch Elements (ROPE) that attempts to solve the problems of memory latency and conditional jumps without hardware scheduling. ROPE consists of a pipelined CPU or very-large-instruction-word data path with a new instruction prefetching mechanism that supports general multi-way conditional jumps. To get high-performance without scheduling hardware, ROPE relies on an optimizing compiler based on a global code transformation technique (Percolation Scheduling). This paper describes both the promise and the limitations of ROPE.